1. Technical Field
Various embodiments of the present invention relate to semiconductor apparatuses and related methods. In particular, certain exemplary embodiments relate to a semiconductor apparatus and a probe test method thereof.
2. Related Art
A semiconductor apparatus, in particular, a memory apparatus has a memory core for storing data. Logic circuits for ensuring the normal operation of the semiconductor apparatus and for performing tests are generally disposed in a peripheral region of the memory core. The logic circuits for performing tests may include a probe test logic circuit for measuring the internal voltage levels or for performing a probe test to detect a defective cell. The probe test is generally performed when a semiconductor chip is in a wafer form.
FIG. 1 is a schematic view illustrating the layout of a chip of a conventional semiconductor apparatus. In the chip shown in FIG. 1, a probe test logic circuit 15 for performing a probe test of the chip is disposed in a peripheral region PERI of the chip. Logic circuits 11, 12, 13 and 14 for ensuring the normal operation of the semiconductor apparatus are also disposed in the peripheral region PERI of the chip. Peripheral region PERI is surrounded by a memory core comprised of one or more memory banks BANK0 through BANK7, and the edge regions of the chip serve as scribe lanes Scribe Lane. After the probe test of the chip is performed on the wafer, a semiconductor apparatus can be manufactured by cutting the wafer along the scribe lanes in the edge regions and packaging the chip.
A probe test logic circuit for performing the probe test may be useless except when the chip is tested on the wafer. However, since the probe test logic circuit is conventionally disposed in the peripheral region PERI where a logic circuit for ensuring the normal operation of the semiconductor apparatus and bondings of pads are located, the probe test logic circuit could not be easily removed.
Meanwhile, a three-dimensional semiconductor apparatus that stacks and packages a plurality of chips in a single package has been recently developed to enhance the degree of integration of a semiconductor apparatus. Because two or more chips are vertically stacked, such a three-dimensional semiconductor apparatus can attain an increased degree of integration in the same amount of space. Moreover, a Through Silicon Via (TSV) method, which forms a silicon via through a plurality of vertically stacked chips to electrically connect one another, has been in use recently. Since a semiconductor apparatus that uses the TSV method vertically passes through and electrically connects the stacked chips, the packaging area of the semiconductor apparatus can be efficiently decreased when compared to a semiconductor apparatus that electrically connects each of the chips using bonding wires disposed in the edges of the chips.
When TSVs are used, although a single semiconductor apparatus can be formed by stacking a plurality of chips having the same structure, a single semiconductor apparatus is generally composed of one main chip for controlling the entire operation of the semiconductor apparatus and a plurality of slave chips for storing data. The main chip, as shown in FIG. 1, may include both a logic circuit and a pad disposed in the peripheral region PERI of the chip. The main chip may further include a memory core. For the slave chip, it may be sufficient to include only a memory core, a logic circuit for repair, and a logic circuit for TSV connection.
In order to improve the price competitiveness of a semiconductor apparatus, it may be important to increase the number of chips that are disposed on a single wafer. However, manufacturing the slave chips according to the above-mentioned conventional methods may not permit such an increase in the total number of chips on a wafer and therefore is economically inefficient.